A Fan-Out Wafer Level Package (FO-WLP) commonly includes a molded body in which at least one semiconductor die is embedded. Multiple FO-WLPs can be bonded and interconnected in a stacked relationship to produce a so-called “three dimensional microelectronic package” or, more simply, a “3D package.” Each FO-WLP of a set of stacked FO-WLPs of a 3D package may be referred to herein as a “FO-WLP core” to avoid confusion in terminology between the FO-WLPs and the 3D package itself. In the case of many 3D packages, interconnection between the stacked FO-WLP cores is accomplished utilizing one or more Ball Grid Arrays (BGAs), Through Substrate Vias (TSVs), backside Redistribution Layers (RDLs), and the like. The inclusion of such features in a 3D package can, however, add undesired cost and complexity to the manufacturing process. Additionally, the presence of an intervening BGA between stacked FO-WLP cores increases the overall height or thickness of the 3D package. For these and other reasons, 3D packages have been developed that utilize electrically-conductive traces deposited on the package sidewalls to interconnect stacked FO-WLP cores. For example, the electrically-conductive traces (referred to herein as “side connect traces”) can electrically couple interconnect lines contained within different stacked FO-WLP cores and extending to one or more sidewalls of the 3D package. Advantageously, such electrically-conductive traces can be produced in a cost effective manner and without increasing overall package thickness.
While providing the above-noted advantages, 3D packages including side connect traces remain limited in certain respects. For example, and without implicit admission that any such problems or drawbacks have been recognized by others in the art, the present inventors have determined that discontinuities or other structural defects can occur within the side connect traces when deposited over the sidewalls of a molded body included within a FO-WLP core. In particular, the side connect traces can be interrupted by cavities or pockets formed in the sidewalls of the molded FO-WLP body due to the dislodgement of hard particles during singulation of the larger molded panel from which the molded body is produced. Such structural defects can increase electrical resistance across the side connect traces or, perhaps, fully sever the electrically-conductive paths provided by the traces. As a further drawback associated with conventional 3D packages, the surface area of the interconnect lines exposed at the package sidewalls and contacted by the side connect traces is often relatively limited due to design restrains placed on interconnect line size. The electrical resistances across the interconnect line-side connect trace interfaces may consequently be undesirably high, while the mechanical strength of these interfaces may be undesirably limited.
For simplicity and clarity of illustration, the drawing figures illustrate the general manner of construction, and descriptions and details of well-known features and techniques may be omitted to avoid unnecessarily obscuring the exemplary and non-limiting embodiments of the invention described in the subsequent Detailed Description. It should further be understood that features or elements appearing in the accompanying figures are not necessarily drawn to scale unless otherwise stated. For example, the dimensions of certain elements or regions in the figures may be exaggerated relative to other elements or regions to improve understanding of embodiments of the invention.